Method and device for reading mpeg recorded data transmitted on an ieee 1394 bus

ABSTRACT

The process is characterized in that it comprises:  
     a step of reading tags recorded together with the packets, these tags defining the instants of arrival of the data packets to be recorded, on the basis of a tagging clock ( 8 ),  
     a step of comparing the tags with values counted ( 9 ) on the basis of a transfer clock ( 8 ) for determining the instants of transfer on the bus of the data read from the record carrier,  
     the frequencies of operation of the said tagging and transfer clocks being such that the maximum deviation between these frequencies, added to the maximum drift of the MPEG system clock, is, in proportion to the nominal values, of the order of or less than the drift of the system clock specified in the standard.  
     Application to the storage of MPEG data.

[0001] The invention relates to the recording and the reading of therecorded data coded according to the MPEG 2 standard or according to theDV standard, acronyms for the expressions Motion Picture Expert Group etDigital Video, transmitted on an IEEE 1394 bus. It pertains for exampleto the recording of DSS (standing for Digital Satellite System) dataoriginating from a satellite receiver, of DV data originating from adigital camcorder etc., these data travelling over an IEEE 1394 bus fortheir recording or their decoding by a digital decoder.

[0002] The appearance of novel digital audiovisual equipment such asvideo recorder, camcorder, multimedia computer etc. is now making theuse of a high-speed link between such equipment indispensible.Home-automation networks are constructed around a fast IEEE 1394 serialbus to which such equipment are subscribers.

[0003] A bus can comprise up to 63 participants called nodes, and up to1023 buses can be deployed in one and the same system. Each nodecomprises three main functional components, a physical interface layer(called the PHYSICAL LAYER) which carries out the interfacing with thecable, the arbitration of the bus and an active repeater function, alink control layer (called the LINK LAYER) which assembles anddisassembles the data packets and takes charge of the exchangeprocedures, a host controller which manages the higher layers of thecommunication protocol (called the TRANSACTION LAYER).

[0004] Several types of audio and video data, for example MPEG 2, DV,DSS etc. are exchanged over the 1394 bus, the subscribers being able todeal with these various standards.

[0005] The audio and video train data required to be transmitted in realtime are exchanged in isochronous mode. A bus will incorporate a rootnode (as it is known in the standard), as well as a manager ofisochronous resources and a bus manager, which will be defined duringthe bus initialization phase. The isochronous resources manager isresponsible for allocating the isochronous resources (in terms ofbandwidth) for the entire session, on the basis of elementary cycles of125 microseconds on the bus. However, this does not make it possible toguarantee a low level of jitter such as may be required during thetransmission of data, for example a TS transport train to an MPEGdecoder, as recalled hereinbelow.

[0006] International standard ISO/IEC 13818-1 relating to the coding ofaudio and video data of MPEG 2 type, as far as systems are concerned,describes a synchronization model for the complete chain, that is to sayas regards the coding, transmission, decoding and displaying of the MPEGtype images. The recovery of the system clock, at the decoder level, isperformed for example by locking, via a phase-locked loop, the values ofthe local clock to the reference clock values transported by the PCR ofan incoming TS stream. The instant of arrival of the PCR field must notcause a drifting of the system clock such as reproduced in the decoder,of more than 30 ppm, the precision imposed by the ISO/IEC 13818-1international standard.

[0007] An audiovisual layer has been defined so as to allow the receiverto compensate for the variations in transmission time which areintroduced by the 1394 bus. It is specified by IEC standard 61883. A12-byte header, in the case of MPEG 2 data, containing a “time marker”(also known as a time stamp) is appended to the data packets, packetsconsisting of 188 bytes in the case of this MPEG 2 standard.

[0008] Before transmission on the bus, at the input of the 1394interface, the packets are marked or stamped, on the basis of the clockof the 1394 circuits whose precision, according to the standard, is 100ppm. The audio video packets are stored in the FIFO memory of the 1394interface, each packet receives a temporal sample, in fact a header,upon its arrival in the memory. This memory acquires a certain number ofpackets over the duration of 125 microseconds, depending on the bit rateat the input. When the 125-microsecond synchronization signal (“cyclestart”) is triggered, these packets are transmitted over the 1394 bus,following one another.

[0009] After receipt of the packets originating from the bus, at theoutput of the 1394 interface, the marker is read and compared with thecontent of a local counter so as to define what will be the instant ofpresentation of the packet. This temporal sample makes it possible torecreate the temporal distribution that existed at the input of theFIFO. The local counter is synchronized at each cycle start with theclock of the root node which generates the reference period of 125microseconds.

[0010] In the case of a direct link, that is to say of a simple transfervia the 1394 bus, the deviation between the stamping instant and theinstant of reading of the tag is of the order of a hundred microsecondsor so. The writing or more precisely the tagging of the data as well asthe reading of this tag are performed on the basis of different localclocks which are however simultaneously synchronized every 125microseconds with the master clock of the root node. The writing and thereading being quasi-instantaneous, the effects due to jitter or driftintrinsic to the IEEE1394 bus synchronization mechanism and to theprecision of its clock system do not therefore result in a drift in thedistribution of the packets over time, at the output of the 1394interface. Consequently, the 1394 bus does not modify the bit rate andthis temporal marking according to the IEC 61883 standard resolves theproblem of loss of temporal distribution of the MPEG 2 packets duringtransmission over the 1394 bus.

[0011] However, when a mass storage is associated with the audiovisualequipment, when the TS stream transmission chain is “cut”, for exampleowing to a recording of the compressed data of this stream on a harddisk for subsequent reading by the decoder, this specific problem ofdrift persists when the data travel via the 1394 bus.

[0012] The use of tagging relating to the 1883 layer, for recording onthe carrier, does not make it possible to resolve the problem owing tothe precision of the 1394 synchronization clock, which is of the orderof 100 ppm. The instant of stamping of the data is different from theinstant of reading of these data from the hard disk. There is drift inthe output bit rate of the 1394 interface owing to the new temporaldistribution of the packets over time related to the alterations in theclock frequency.

[0013] It may also be remarked that the root node during recording maybe different from that during reading. Consequently, the synchronizationof the clock during tagging may be achieved with regard to a differentmaster clock from that during the reading of the tag.

[0014] This drift in the bit rate and therefore in the instants ofarrival of the PCRs to which the 27 Mhz local clock synchronizes causesa frequency drifting of this clock. Consequently, in the longer orshorter term, a drying up or an overflowing of the buffer of the MPEGdecoder occurs resulting in a defect in the screening of the images onthe receiver, for example an image freeze appears recurrently.

[0015] An overly large shifting of this synchronized clock may alsoimpair the quality of the chrominance signals extracted from thesubcarrier.

[0016] Modifying the 100 ppm precision of an item of equipment would notmake it possible to resolve the problem since any item of equipment maybe declared root node during the writing and then during the reading ofthe data of the hard disk.

[0017] Thus, if the compressed data are not transmitted directly to adecoder but are recorded on a record carrier, for example a hard disk,so as, subsequently, to be read, by way of a 1394 bus, by the decoder,problems of drifting persist, sooner or later causing in a recurrentmanner a defect in the displaying of the images.

[0018] A known mode of operation called “pull” in which the bit rate fortransferring data from the hard disk to the decoder can be “commanded”by the decoder, for example as a function of the degree of fill of thebuffer of the decoder makes it possible to avoid any drying up oroverflowing of this buffer. In this mode, the problems of clockprecision are less crucial, an overly large drifting of the clock of thedecoder, owing to a drift in the bit rate, being corrected by regulatingthe bit rate of the stream when reading, by the decoder, as a functionof the fill level of the buffer of the decoder. This mode of operationis not however possible in the case of a TS stream recording which doesnot allow direct memory accesses (DMA) by the decoder. As far as therecording at the PES packet level is concerned, it does not allow thetransferring of these data over the 1394 bus.

[0019] The aim of the invention is to alleviate the aforesaid drawbacks.

[0020] Its subject is a process for reading from a record carrier audioand video data coded in the form of packets according to the MPEGstandard, for their transmission to a decoder by way of a bus, thesepackets having previously been recorded together with tags defining, onthe basis of a tagging clock, instants of reception from the bus of thepackets to be recorded, characterized in that it comprises:

[0021] a step of reading the tags recorded together with the packets,

[0022] a step of comparing the tags with values counted on the basis ofa transfer clock for determining the instants of transfer on the bus ofthe data read from the record carrier,

[0023] the frequency of operation of the transfer clock being such thatthe maximum deviation between the frequencies of the tagging clock andof the transfer clock, added to the maximum drift of the MPEG systemclock, is, in proportion to the nominal values, of the order of or lessthan the drift of the system clock specified in the standard.

[0024] According to a variant, the process is characterized in that thetagging clock and the transfer clock are one and the same clock and inthat the frequency of operation is such that its maximum drift, added tothe maximum drift of the system clock is, in proportion to the nominalvalues, of the order of or less than the drift of the system clockspecified in the standard divided by two.

[0025] The subject of the invention is also a reading device for theimplementation of the process comprising a record carrier and a readinginterface circuit for the reading and the transferring of the data fromthe record carrier to a bus, characterized in that it comprises at leastone transfer clock for transferring the data read, such that the maximumdeviation between the frequency of the tagging clock and the frequencyof the transfer clock, added to the maximum drift of the MPEG systemclock, is, in proportion to the nominal values, of the order of or lessthan the drift of the system clock specified in the standard.

[0026] According to a variant, the device is characterized in that thetagging clock and the transfer clock are one and the same clock and inthat its frequency of operation is such that its maximum drift, added tothe maximum drift of the system clock is, in proportion to the nominalvalues, of the order of or less than the drift of the system clockspecified in the standard divided by two.

[0027] By virtue of the stamping of the packets stored in the recordcarrier on the basis of a specific clock, the risks of drying up or ofoverflowing of the buffer of the decoder are reduced to the minimum.

[0028] The main advantage of the invention is that it allows perfectcompatibility in respect of the storing and transferring of signals ofDV or MPEG type through a 1394 bus.

[0029] The characteristics and advantages of the present invention willbecome better apparent from the following description, given by way ofexample and with reference to the appended figures which represent:

[0030]FIG. 1, a receiver linked to a recording device,

[0031]FIG. 2, a write interface circuit,

[0032]FIG. 3, a read interface circuit.

[0033] A configuration of a device for recording compressed data on arecord carrier linked to a satellite receiver through a 1394 bus isrepresented in FIG. 1. A receiver 1 equipped with a 1394 interfacecircuit receives a train of audiovideo data compressed according to theMPEG 2 standard originating from a satellite transmission, called the TStransport train in the standard (the acronym standing for TransportStream). The signal received by the receiver is, among other things,demodulated so as to provide a baseband signal. This transport streamcomprises several programmes. It may be transmitted as is or else afterfiltering selecting only the packets corresponding to a chosenprogramme.

[0034] A 1394 interface circuit incorporated into the receiver makes itpossible to transmit this data stream over the 1394 link. This circuitconsists, according to the nomenclature of the standard, of a “linkcontrol” layer (LINK) 2 and of a physical interface layer (PHY) 3. Itmakes it possible, among other things, to carry out the tagging of thepackets according to the IEC 61883 standard. The data are transmitted byway of a 1394 port. The recording device 4 comprises a hard disk 10 andan interface circuit of the hard disk 4 linked to the 1394 bus and tothe hard disk.

[0035] This interface circuit 4 comprises a PHI circuit 5, a LINKcircuit 6, a write interface circuit 7, a read interface circuit 9 and aclock circuit 8.

[0036] The data arrive, by way of a 1394 port, on a PHY circuit 5 and aLINK circuit 6 in accordance with the 1394 standard. They aretransmitted on the audiovideo output port of the LINK circuit at theinstants corresponding to the tagging of the packets. The audiovideoport is linked to the input of a write interface circuit 7 which stampsthe data in accordance with the invention. The hard disk interfacecircuit 4 is linked to a hard disk 10. It transmits the stamped data tothe hard disk for their recording.

[0037] The hard disk 10 is linked to an input of the interface circuit 4for the reading of the data. A read interface circuit 9 will read thedata on this input so as to transmit them to the input audiovideo portof the PHI circuit 6. These data are then sent to the 1394 bus via thePHY circuit 5 and the 1394 port.

[0038] A clock 8 feeds each of the interface circuits 7 and 9.

[0039] Writing of the Data

[0040] The write interface circuit 7 is now described in greater detailwith the aid of FIG. 2.

[0041] The audio and video data accompanied by validation and packetstart signals and by a 10 Mhz synchronization clock originating from theaudiovideo output port of the LINK circuit 6 are present at the input ofthe write interface circuit 7. The data are stored in a packet memory11. The clock signal increments a write counter 12 which commands thewriting to the packet memory 11. The packet start signal allows theresetting of this counter 12 to zero. A read counter 13 commands thereading of the packet memory 11, synchronizes a multiplexer 17 andcontrols the writing to a buffer memory 18 for the transmission andrecording of the data. On an input, this counter 13 receives aninformation item regarding the length of the packets, namely 188 bytesin the case of MPEG 2 type data, 131 bytes in the case of DSS type dataand 480 bytes in the case of DV type data.

[0042] The packet memory has the role of ensuring that the data receivedare whole packets and, if not, of transmitting packets with the rightlength, by appending padding bits.

[0043] The stamping of the data according to the invention is achievedon the basis of a specific clock which is a high frequency oscillator 8,for example at the frequency of 40 Mhz and whose conditions of stabilityover time are specified between 1 ppm and 15 ppm as will be explainedlater. This oscillator is linked to the clock input of a counter 14. Itis also linked to a packet start detection circuit 15 and a captureregister 16 of the temporal marker, for the synchronization of thesecircuits. The counter 14 is paced by the clock 8 and transmits thecounting words to the register 16. When the packet start signal, whichis transmitted to the packet start detection circuit 15, is received,this circuit transmits a validation signal, synchronized with the clock8, to the register 16 which stores the counter output at this instant.The detection circuit 15 makes it possible to retrieve the start of apacket in the case where this signal is not otherwise transmitted and tosample it so as to render it synchronous with the high frequency clock8. The value stored by the register 16 is transmitted to a multiplexer17 which also receives the data output by the packet memory 11. The readcounter 13 commands the multiplexer which transmits at its output, firstof all the tag corresponding to the instant of arrival of the packetstart in the packet memory and then the data of this stored packet.These data pass through a recording buffer memory 18 before beingtransmitted on the output of the interface 7 for their storage, in theform of an audiovideo file, by the hard disk 10 linked to this output.

[0044] Reading of the Data

[0045] The interface circuit 9 is now described in greater detail withthe aid of FIG. 3.

[0046] The hard disk 10 is linked to an input of the read interfacecircuit 9 to provide the recorded data. These data at the input of thiscircuit travel via a read buffer memory 19, then are transmitted to apacket memory 20 and a tag extraction circuit 21. The audiovideo dataoriginating from the hard disk are recorded in the packet memory 20whereas the tagging data are extracted so as to be stored by the tagextraction circuit 21. These tagging data are those appended to theaudiovideo data by the circuit 7, for each packet, as indicated above.The information item relating to the length of a packet is transmittedto the extraction circuit 21, the tag to be extracted being received atthe packet rate.

[0047] The extraction circuit 21 transmits the tags to a restorationcounter 23 and to a register for storing the temporal tag 22, insynchronization with the clock 8 received by the circuit. It alsotransmits a loading command signal to the restoration counter upon theopening of the file, this counter then loading the first temporal tagread during the opening of the file so as to initialize itself. It alsotransmits a data consideration signal to the storage register 22, duringthe dispatching of an extracted temporal tag. The tag is then loaded bythe register in synchronization with the clock signal 8 also received bythis register.

[0048] The clock input of the counter 23 receives the signals of theclock 8. The output of the counter 23 is transmitted to a comparator 24which on a second input, originating from the storage register 22,receives the temporal tag of the packet which is undergoing storage inthe packet memory 20. Upon equality, and synchronized with the clocksignal 8 received by the circuit, a read command signal is transmittedby the comparator 24 to a packet counter 25. On receipt of this signal,the counter triggers the reading of a number of bytes corresponding to apacket. This packet counter receives the information item relating tothe length of a packet. During the reading of the data of the packetmemory 20, the counter 25 actuates the reading of a new packet of theread buffer memory 19 and the writing of this packet to the packetmemory 20. The clock input of the packet counter is fed by theaudiovideo clock signal originating from the LINK interface 6 so as tosynchronize the transmission of the data. The audiovideo dataoriginating from the packet memory 20 as well as the corresponding validclock signals, packet start signals and data originating from the packetcounter 25 are supplied at the output of the interface circuit 9.

[0049] Thus, the restoration counter 23 is initialized with the tag ofthe first packet read from the file of the hard disk. In the transientphase, the first packet is stored in the packet memory and readimmediately, hence transmitted immediately to the audiovideo input portof the LINK circuit 6. After storage followed by immediate transmissionof the first packet, the tag of the second packet is extracted andloaded into the register 22 while the second packet is stored in thepacket memory. The counter 23 runs at the frequency of the precisionclock 8 and when the counting value is equal to the value of the secondtag, the comparator 24 transmits a signal for triggering the packetcounter 25 for the reading and the transmission to the audiovideo inputport of the LINK circuit 6 of the number of bytes corresponding to apacket. And so on and so forth for each reading of a new packet.

[0050] The packet counters' synchronization clocks are transmitted bythe audiovideo port of the LINK circuit. The could equally well beconstructed on the basis of the 40 Mhz high frequency oscillator, thesignal being for example divided by 4 to provide a 10 Mhz clock feedingthese counters.

[0051] The example describes the use of one and the same clock 8 by thewrite interface circuit and the read interface circuit for the taggingof the data during their recording and the transferring of the data readover the 1394 bus. It would also be conceivable to envisage theimplemention of the circuits on the basis of two separate clocks(oscillators), a tagging clock and a transfer clock. It is thennecessary to take account of additional constraints relating to theseclocks. Specifically, during the utilization of a common clock, onlyvery good stability of the frequency is required, stability over time,with temperature etc. However, good precision is not indispensible sincerelative dating of one packet with respect to another is involved. Inthe case where two independent clocks are used, one for tagging and onefor transfer, this relative dating depends also on the frequencydeviation between the two clocks. Consequently, the precision of theclocks with respect to their nominal value must also be specified. Thefrequency of the second clock must for example be guaranteed inside therange within which the frequency of the clock for tagging may alter. Itis also possible to specify very precise nominal frequencies for each ofthe clocks, for example to within 1 ppm and drifts of 15 ppm maximum foreach of them.

[0052] This specification of the clock in terms of maximum drift of 15ppm, gives a maximum deviation of 30 ppm between recording and reading,neglecting the deviations between the nominal frequencies in the casewhere two clocks are used. If, however, several successive storages ofthe data are envisaged, better precision is required, the error possiblyaccumulating with each stamping and hence with each recording. Forexample, a precision of the order of 1 ppm then allows some fifteensuccessive recordings.

[0053] The frequencies of operation of the clocks for tagging (alsocalled recording clocks) and for transfer are such that the maximumdeviation between these frequencies, proportionally speaking, is roundabout the tolerance in the system clock, specified at ±30 ppm in theMPEG2 standard. It was therefore previously assumed that the frequencyof the system clock has a maximum drift of ±1 ppm, allowing a drift of±30 ppm in the mean rate at the input of the decoder (reading of thePCR) corresponding to a drift of 15 ppm maximum for the tagging andtransfer clocks.

[0054] In the case where one desires compatibility with any type ofcoder and hence by assuming a maximum drift of the system clock of ±30ppm, the frequencies of the tagging and transfer clocks must not deviateby much more than 1 ppm. These are of course indicative values andoperation will be all the better the closer one comes to these values.

[0055] Stated otherwise, the frequencies of operation of the tagging andtransfer clocks are such that the maximum deviation between thesefrequencies, added to the maximum drift of the MPEG system clock, is, inproportion to the nominal values, of the order of or less than the driftof the system clock specified in the standard.

[0056] The data stream travelling over the 1394 bus is for example anMPTS (Multiple Program Transport Stream) transport stream comprisingseveral programmes, such as defined in the MPEG 2 standard. Thecollection of programmes transported may then be recorded in the harddisk. It may also be an SPTS (Single Program Transport Stream) transportstream obtained by filtering the MPTS stream in the MPEG 2 decoder alsocalled the “parsed” stream. The 188-byte packets are then receivedirregularly at the input of the 1394 interface and one then reasons interms of mean rate. It is this program alone which is recorded in thehard disk.

[0057]FIG. 1 describes a 1394 link between a receiver and a recordingdevice. The latter could equally well, without departing from the fieldof the invention, be incorporated into the receiver, the TS data thenbeing transmitted directly to the hard disk interface circuit, withouttravelling via a 1394 bus and hence without passing through the LINK andPHI circuits for their recording.

[0058] The DV signals do not need such precision at the decoding level.Simply the device implemented for the MPEG type signals may also be usedfor the tagging of the DV packets for their recording and reading fromthe record carrier.

1. Process for reading from a record carrier audio and video data codedin the form of packets according to the MPEG standard, for theirtransmission to a decoder by way of a bus, these packets havingpreviously been recorded together with tags defining, on the basis of atagging clock (8), instants of reception from the bus of the packets tobe recorded, characterized in that it comprises: a step of reading thetags recorded together with the packets, a step of comparing the tagswith values counted (9) on the basis of a transfer clock (8) fordetermining the instants of transfer on the bus of the data read fromthe record carrier, the frequency of operation of the transfer clockbeing such that the maximum deviation between the frequencies of thetagging clock and of the transfer clock, added to the maximum drift ofthe MPEG system clock, is, in proportion to the nominal values, of theorder of or less than the drift of the system clock specified in thestandard. 2 Process according to claim 1, characterized in that thetagging clock and the transfer clock are one and the same clock (8) andin that the frequency of operation is such that its maximum drift, addedto the maximum drift of the system clock is, in proportion to thenominal values, of the order of or less than the drift of the systemclock specified in the standard divided by two. 3 Process according toclaim 1, characterized in that the system clock has a tolerance ofaround ±1 ppm, the nominal frequency of the tagging and transfer clock(8) a tolerance of around ±1 ppm and in that the drift of each clocklies in a range of ±15 ppm. 4 Process according to claim 2,characterized in that the system clock has a tolerance of around 1 ppm,in that the drift of the tagging and transfer clock (8) lies in a rangeof ±15 ppm. 5 Process according to claim 1 or 2, characterized in thatthe data to be recorded originate from a 1394 bus. 6 Process accordingto claim 1 or 2, characterized in that the data to be recordedcorrespond to the TS stream originating directly from the receiver (1)without travelling over a 1394 bus. 7 Process according to claim 1,characterized in that the data read are also data of DV and/or DSS type.8 Process according to claim 3 or 4, characterized in that the drift isaround 1 ppm so as to allow successive recording/reading operations. 9Process for recording on and for reading from a record carrier audio andvideo data in the form of packets, coded according to the MPEG standard,for their transmission to a decoder by way of a bus, characterized inthat it comprises: a step of tagging the packets on their reception fromthe bus, on the basis of a tagging clock (8), so as to define theinstants of arrival of the data packets, a step (7) of recording thepackets received and the tags, a step of reading the tags and ofcomparing with values counted (9) on the basis of a transfer clock (8)so as to define the instants of transfer on the bus of the data readfrom the record carrier, the frequencies of operation of the saidtagging and transfer clocks being such that the maximum deviationbetween these frequencies, added to the maximum drift of the MPEG systemclock, is, in proportion to the nominal values, of the order of or lessthan the drift of the system clock specified in the standard. 10 Readingdevice for the implementation of the process according to claim 1comprising a record carrier (10) and a reading interface circuit (9) forthe reading and the transferring of the data from the record carrier toa bus, characterized in that it comprises at least one transfer clock(8) for transfering the data read, such that the maximum deviationbetween the frequencies of the tagging clock and of the transfer clock,added to the maximum drift of the MPEG system clock, is, in proportionto the nominal values, of the order of or less than the drift of thesystem clock specified in the standard. 11 Device according to claim 10,characterized in that the clock having served for the tagging and thetransfer clock (8) are one and the same clock and in that its frequencyof operation is such that its maximum drift, added to the maximum driftof the system clock MPEG is, in proportion to the nominal values, of theorder of or less than the drift of the system clock specified in thestandard divided by two.